Conventionally, the interconnection between device active areas formed in a semiconductor substrate is provided by conductive metal layers including conductive traces or lines formed in multiple levels of the substrate and interconnected by conductive vertical vias or plugs. First level vias (also referred to as windows) provide electrical connection to the device active areas. Vias at higher levels interconnect adjacent levels of conductive metal traces. Forming these conductive traces and conductive vias requires the use of various process steps, including: polishing, cleaning, deposition, patterning, masking and etching.
Recently, great interest has been shown in the use of copper and copper alloys for metallization within semiconductor devices. Compared with aluminum and its alloys, copper has both beneficial electromigration resistance and a relatively low resistivity of about 1.7 micro-ohm-cm. Unfortunately, copper is a difficult material to etch. Consequently, single and dual damascene processes, in which the copper is deposited in trenches formed in dielectric layers, have been developed to simplify the use of copper interconnects and eliminate metal etching steps. The damascene structures are also referred to as inlaid metallization interconnects. These damascene processes can also employ aluminum alloys in lieu of copper as the conductive material.
The dual damascene structure includes conductive runners substantially parallel to the semiconductor substrate surface and perpendicular conductive vias for interconnecting overlying conductive runners. The first level conductive via (also referred to as a conductive window) contacts an underlying device active area rather than an underlying conductive runner. Thus the dual damascene conductive via provides the same function as the plug structure in a traditional interconnect system.
The conductive vias and the interconnecting conductive runners are formed by forming via openings and interconnecting horizontal trenches within a dielectric layer of the device. The first level vertical openings are typically referred to as windows and the upper layer openings are referred to as windows. When the conductive material is copper, a barrier layer is formed in the openings to prevent copper diffusion from the conductive regions into the dielectric. It is known that without a barrier, copper easily migrates into the dielectric layer and can cause leakage current. These leakage currents can short metallization regions and degrade device performance.
Following the barrier layer formation, a seed layer comprising the same material as the conductive material is formed over the barrier layer to promote electrodeposition of the conductive material. During the electrodeposition step, copper is simultaneously formed in the vias and the trenches and typically overfills the trenches. A chemical-mechanical polishing step removes the copper overfill. In a single damascene process the conductive material is deposited in the vias during a first processing step, and the conductive runners are filled with conductive material during a second processing step.
The dual damascene process eliminates the need to form a conductive plug structure in the vias or windows and an overlying conductive layer during separate processing steps, as taught by the conventional interconnect system.
One disadvantage of the prior art dual damascene process is illustrated with reference to FIG. 1. A dual damascene conductive runner 10 and conductive via 12 are formed in a dielectric layer 16 overlying a semiconductor substrate 18. A dielectric layer 20 is formed over the dielectric layer 16, and a via opening 22 formed therein.
After forming the via opening 22, a pre-barrier layer sputter cleaning process is performed to remove any copper oxide that might have formed on a surface 23 of the conductive runner 10 exposed through the via opening or window 22. Copper oxide can form on the surface 23 during several of the normal fabrication steps performed in the processing facility. The copper oxide can form after the chemical/mechanical polishing (CMP) step that removes copper overfill as the wafer is transported from the CMP processing tool to the deposition tool. The copper oxide can also form during subsequent annealing steps or during deposition of the dielectric layer 20. Typically, the dielectric layer 20 is formed from an oxide-based material and therefore may include oxygen-containing chemistries that promote the oxide formation. The copper oxide can form on the surface 23 during formation of the via opening 22 by etching processes that include oxygen chemistries. The copper oxide can develop after formation of the via opening 22 due to interactions between the copper with the ambient oxygen. It is advantageous to remove the copper oxide to improve the conductivity between the conductive runner 10 and the overlying conductive surface, which is typically a conductive via according to the dual damascene process.
According to the prior art, during the pre-sputter cleaning process, argon ions are directed at the surface 23 to sputter away the copper oxide. However, if the sputtering/cleaning process is not terminated immediately after all the copper oxide has been removed or if the copper oxide is non-uniform across the exposed surface, then copper from the underlying conductive runner 10 is sputtered off and deposited onto sidewalls 24 of the via opening 22, as illustrated by an arrowhead 26. As discussed above, this copper contaminates and diffuses into the dielectric layer 20, potentially causing short circuits and degrading device performance.
According to conventional dual damascene processing, after the pre-sputter clean step copper or another conductive metal is formed in the via opening 22 for interconnecting the conductive runner 10 with a conductive runner subsequently formed in the upper region of the dielectric layer 20.
A known technique for avoiding the copper contamination of the dielectric layer requires the formation of a capping layer over the copper conductive layer prior to the cleaning step. See for example, U.S. Pat. No. 6,114,243 (Gupta, et al). After the conductive runner 10 is formed and the upper surface of the dielectric layer 16 is planarized to remove copper overfill, a recess (not shown) is etched into the conductive runner 10 and filled with a conductive capping layer. The material of the capping layer fills the recess and extends over the upper surface of the dielectric layer 16 (referred to as the field region). In subsequent masking and etching steps the capping material is removed from all regions of the upper surface except within the recess. The overlying dielectric layer 20, via opening 22 and trenches (not shown) are then conventionally formed by etching processes. The capping layer prevents copper contamination onto the sidewalls 24 during these etching steps.
Although this described prior art technique limits copper sputtering onto the via opening sidewalls during the etching process, it is desired to simplify the process and lower the cost by avoiding the need for multiple additional masking, patterning and etching steps as taught by Gupta et. al.